Microprocessors are being built with an increasing number of electronic components packed in a relatively small chip space. Issues of power consumption and dissipation come to fore due as the amount of electronic components in a microprocessor increases. Power dissipation and consumption affect design choices and operating conditions for microprocessors. Hence, there is a need to minimize power dissipation and consumption in microprocessors. In the following, unless specifically qualified, the term “power” is used to subsume both the “dissipation” and “consumption” aspects of power parameters.
There is a distinction between the average power and maximum power dissipation. Average power refers to power averaged over a set of applications or programs, typically run by the customer. Saving the average power reduces the energy cost in wired applications, and prolongs the battery life in portable applications. Maximum power is power dissipated over a segment of code that utilizes the maximum number of resources in the microprocessor. The maximum power sets a requirement on the power dissipating capabilities of the package, and the current delivery capabilities of the power distribution system. Therefore the maximum power has a large impact on the cost of a microprocessor.
There exist several techniques for reducing power in components or resources of a microprocessor. Clock gating is one such technique. Clock gating can only save the dynamic or switching component of power. Another power-saving technique is called data gating. Data gating involves insertion of transition barriers at the inputs of microprocessor components. These transition barriers are typically implemented as either AND or OR logic gates. On cycles when the microprocessor component is not used, the transition barriers prevent the inputs to the component from switching, which results in saving the dynamic or switching power inside the data-gated component. Like clock gating, data gating can only save the dynamic or switching power, but not leakage.
Power gating (also referred to as Vdd-gating) is one another known power saving technique which reduces both the dynamic and leakage power components. Unlike clock gating, Vdd-gating requires multiple clock cycles to activate a Vdd-gated resource which calls for a more sophisticated control mechanism. A Vdd-gated resource must remain gated for a minimum number of cycles (typically tens of cycles) in order to amortize the energy overhead associated with the process of activation and deactivation of the resource,
One approach to controlling the gating of microprocessor resources involves Reactive Gating (RG) techniques. These RG techniques are used to control the maximum temperature of the chip and/or the maximum current drawn by the microprocessor core or the chip. RG techniques use a set of temperature or current sensors that generate signals for gating microprocessor resources if the temperature (or current consumption) sensed by one of the sensors exceeds a threshold. The threshold is set below the limit of the power dissipating capabilities of the package or below the current delivery capabilities of the power delivery system.
RG techniques do not allow relaxing the requirements on the power or current delivery systems due to threshold based control, and the threshold must be set at a relatively pessimistic or conservative level for reactive mechanism to trigger in time and prevent chip failure. RG techniques make it difficult to predict the performance of the processor core, because the reactive mechanism may trigger during the execution of the program. Further, the triggering mechanism for power saving RG techniques may depend on the operating environment factors such as temperature. This triggering mechanism makes the performance of the microprocessor depend on the operating environment factors.
Some examples of the RG techniques are discussed next. U.S. Pat. No. 6,047,248 and U.S. Pat. No. 5,189,314 to Georgiou, et al., propose techniques to vary processor performance based on the information received from thermal sensors. These RG techniques use reactive throttling techniques which are activated upon feedback from the on-chip monitoring of a set of performance metrics.
Another approach to controlling gating involves pure predictive gating techniques that reduce the average microprocessor core or chip power but do not guarantee any reduction under the maximum power usage or provide any upper bound on the maximum power when all microprocessor resources are fully utilized. As an example of a pure predictive gating technique, U.S. Pat. No. 5,504,908 to Ikeda discloses use of address access information to determine when the processor is in an idle loop. These techniques for controlling gating do not allow any relaxing of the requirements on the power dissipation capabilities of the package or the current delivery capabilities of the power delivery system which impact the cost of the microprocessor. Hence, there is a need for a technique(s) to control dissipation of power and minimize the maximum power in a microprocessor.